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@@ -12,13 +12,40 @@
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- TRNG must init first before any SM2 key generation
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- SM2/SM4/SHA share EDMAC channel — do not nest crypto operations
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-## SPI/DMA Critical Details
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+## SPI/DMA Critical Details (VERIFIED via .map file)
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- `dma_spitran()` binten hardcoded FALSE — interrupt branch is DEAD CODE
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- Must use `dma_spi_LLIReceive()` for continuous async receive
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- LLI `next_lli` points to itself for auto-loop
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-- dmac_isr() reads DMA_STATTFR, sets dma_isr_flag, clears DMA_CLRTFR
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-- SPI1+SPI2+PIT32 share IRQ3 (ISR23)
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-- DMA completion interrupt goes through IRQ4 (dmac_isr)
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+- **`dmac_isr()` from `dmac_drv.c` is DISCARDED by linker — NOT in binary**
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+- **Actual IRQ4 handler = `DMA_IRQHandler` from `libCUni360S_mcc.a(mcc_bsp.o)` at 0x0041b2ac**
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+- **MUST modify `vector_table.h` ISR24** to repoint IRQ4 to our own DMA handler
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+- **Vector table is `void *const` in flash** — `interrupt_setup()` only sets EIC priority, NOT the vector
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+- SPI1+SPI2+PIT32 share IRQ3 (ISR23 = PIT32_SPI1_SPI2_ISR)
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+- DMA completion interrupt goes through IRQ4 (ISR24)
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+- DMAC_INT_NUM = 0x24 = VecTable[36] = ISR24
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+- SPI1 base = 0x70000000, SPIDR offset = 0x12 (verified in spi_reg.h and dmac_drv.c)
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+- SPI instances spaced 0x10000 apart: SPI1=0x70000000, SPI2=0x70010000, SPI3=0x70020000
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+
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+## CRC Hardware (VERIFIED)
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+- Hardware CRC engine does NOT support configurable polynomials
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+- CRC_CR has NO polynomial field — only mode (CRC-8/16/32), source, endianness
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+- **CRC16-CCITT (0x1021) MUST be implemented in SOFTWARE**
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+- CRC0_BASE_ADDR = 0x78000000, CRC1_BASE_ADDR = 0x7c000000
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+
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+## RAM Budget (VERIFIED via .map file)
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+- .data = 2,992 bytes (0xBB0) at 0x00800000-0x00800BB0
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+- .bss = 6,740 bytes (0x1A54) at 0x00800BB0-0x00802604
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+- Total used: 9,732 bytes (14.8%)
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+- Free heap: 47,608 bytes (0xB9F8) from 0x00802604 to 0x0080DFFC
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+- Stack: 8,192 bytes from 0x0080DFFC to 0x0080FFFC
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+- _bss_end = 0x00802604, _end = 0x0080DFFC, STACK_LOCATION = 0x0080FFFC
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+
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+## eFlash Budget (VERIFIED via .map file)
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+- Firmware end: 0x0041C098 (.text_entry + .rodata + .text + .data LMA)
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+- .bin size = 114,840 bytes = 0x1C098 (matches)
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+- Key storage 0x00470000-0x00470800 = 100% free, page-aligned (pages 896-899)
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+- EFLASH_END per alg_drv.h = 0x0047F000 (4KB reserved at top)
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+- 343KB gap between firmware end and key storage region
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## eFlash Key Storage
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- EFLASH_SetWritePermission() is GLOBAL — no per-page protection
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